Regviz

Renesas Electronics /R7FA6M3AH /GLCDC /GR2_FLM6

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as GR2_FLM6

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Renesas Electronics/R7FA6M3AH/GLCDC/GR2_FLM6#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)FORMAT

FORMAT=000

Description

Graphics 2 Frame Buffer Control Register 6

Fields

FORMAT

Data format for accessing graphics data (frame buffer data).

0 (others): Setting prohibited.

0 (000): RGB565 (16 bits/pix)

1 (001): RGB888 (32 bits/pix, 8 bits on the MSB side are invalid)

2 (010): ARGB1555 (16 bits/pix, 1 bit of A is LUT data)

3 (011): ARGB4444 (16 bits/pix)

4 (100): ARGB8888 (32 bits/pix)

5 (101): CLUT8 (8 bits/pix)

6 (110): CLUT4 (4 bits/pix)

7 (111): CLUT11bit/pix)

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data